High data reliability, high speed of memory access, lower power consumption and reduced chip size are features that are demanded from semiconductor memory. In recent years, three-dimensional (3D) memory devices have been introduced. Some 3D memory devices are formed by stacking chips (e.g., dies) vertically and interconnecting the chips using through substrate vias (TSVs). Benefits of the 3D memory devices include shorter interconnects which reduce circuit delays and power consumption, a large number of vertical vias between layers which allow wide bandwidth buses between functional blocks in different layers, and a considerably smaller footprint. Thus, the 3D memory devices contribute to higher memory access speed, lower power consumption and chip size reduction. Example 3D memory devices include Hybrid Memory Cube (HMC), High Bandwidth Memory (HBM), and a wide-I/O dynamic random access memory (DRAM).
For example, High Bandwidth Memory (HBM) is a type of memory including a high-performance DRAM interface chip and vertically stacked DRAM chips. A typical HBM stack of four DRAM chips (e.g., core chips) has two 128-bit channels per chip for a total of eight input/output channels and a width of 1024 bits in total. An interface (IF) chip of the HBM provides an interface with the eight input/output channels, which function independently of each other.
FIG. 1 is a schematic diagram of a TSV array 100 and a test domino switch circuit. The TSV array 100 includes a plurality of TSVs 102, a plurality of redundancy TSVs 104, a plurality of test domino switch circuits (TD-SWs) 106, a plurality of shift registers (SRs) 108, a plurality of control lines 116, and a register line 120.
The TSV array 100 includes TSVs arranged in eight rows and 28 columns. In particular, each of a plurality of TSVs 102 is positioned in a corresponding row of rows 1-8 and a corresponding column of columns 1-27, none of the plurality of TSVs 102 being positioned in the 28th column. Each of a plurality of redundancy TSVs 104(1)-104(8) is positioned in a corresponding row of rows 1-8, and in the 28th column (e.g., last column). Each of the plurality of TSVs 102 and the plurality of redundancy TSVs 104 is coupled to a corresponding one of the plurality of TD-SWs 106. The plurality of SRs 108 are positioned adjacent to a lower side of the TSV array 100. The plurality of SRs 108 are coupled serially by the register line 120. Each of the plurality of SRs 108(1)-108(28) is positioned in a corresponding column of columns 1-28. Each of the plurality of SRs 108 in a corresponding column among columns 1-28 is coupled to one TD-SW among the plurality of TD-SWs in the corresponding column. SRs 108 corresponding to TD-SWs in each of the 28 columns are combined (e.g., grouped) together (e.g., SRs 108(1)-(8) coupled to each of TD-SWs(1,1)-(8,1), respectively are combined together).
Each of the plurality of SRs 108 may store a data value configured to activate or deactivate one of the plurality of TD-SWs 106 corresponding to a respective one of the plurality of TSVs 102. Each data value provided (e.g., transmitted) over the register line 120 may be latched by a corresponding one of the plurality of SRs 108. The data values are shifted serially through the SRs from the SR 108(1) to the SR 108(28), via each of SRs 108(2)-108(27). A respective TD-SW 106 may be activated when the corresponding SR 108 stores a data value corresponding to activation. For example, the TD-SW 106(3,2) is activated when, for example, the SR 108(18) (e.g., the second SR 108 in the third group of SRs 108 which corresponds to the TD-SW in the second row and the third column) stores a data value corresponding to activation.
A data value destined to be latched by one of the SRs 108 to activate or not activate a corresponding TSV is passed at each clock signal from the SR 108(1) to the subsequent one of the SRs 108 until the data value is passed to the one of the SRs 108, and then latched by a corresponding TD-SW to activate or not activate the corresponding TSV. For example, a data value destined to be latched by the SR 108(4) is loaded into the SR 108(1) at a rising edge of a clock signal. Then, the data value destined to be latched by the SR 108(4) is loaded into the SR 108(2) and the data value destined to be latched by the SR 108(3) is loaded into the SR 108(1) at a next rising edge of the clock signal. Then, the data value destined to be latched by the SR 108(4) is loaded into the SR 108(3), the data value destined to be latched by the SR 108(3) is loaded into the SR 108(2), and the data value destined to be latched by the SR 108(2) is loaded into the SR 108(1) at a next rising edge of the clock signal. Then, the data value destined to be latched by the SR 108(4) is loaded into the SR 108(4), the data value destined to be latched by the SR 108(3) is loaded into the SR 108(3), the data value destined to be latched by the SR 108(2) is loaded into the SR 108(2), and the data value destined to be latched by the SR 108(1) is loaded into the SR 108(1), at a next rising edge of the clock signal. The data values for the remaining SRs 108 are serially shifted at each rising edge of the clock signal and provided to the respective SR 108s in a similar manner. All of the plurality of SRs 108 then latch the respective data values when each data value is simultaneously provided to the respective one of the plurality of SRs 108.
When the TD-SW 106(1,1) is triggered, data values originally intended to be provided by all of the plurality of TSVs 102(1)-(27) are instead provided by a combination of remaining ones of the plurality of TSVs 102(2)-(27) and the redundancy TSV 104(1). When the TD-SW 106(1,1) is triggered, a data value originally intended to be provided by the TSV 102(1,1) is provided by the TSV 102(1,2); and a data value originally intended to be provided by the TSV 102(1,27) is provided by the redundancy TSV 104(1). When one of the TD-SWs 106 is triggered, each of the remaining TD-SW 106 in the same row between the triggered TD-SW 106 and the TD-SW 104 in the same row are also triggered. For example, when the TD-SW 106(1,1) is triggered, TD-SWs 106(1,2)-(1,28) are also triggered.
As shown in FIG. 1, a TD-SW(1,3) includes a TSV 102, a D-SW 150, a T-SW 156, and an AND gate 158. The D-SW 150 includes a D-SW normal node N 152 and a D-SW domino node D 154.
The D-SW normal node 152 of the D-SW 150 may be coupled to the TSV 102 via a first node N1. The domino node 154 of the D-SW 150 may be coupled to the TSV 102, via a D-SW line and via the first node N1. A control input of the D-SW 150 is coupled to an output of a respective SR via a second node N2. An input and an output of the T-SW 156 may be coupled, respectively, to a drain voltage/source voltage (Vdd/Vss) signal line 166, and to the TSV 102 via the first node N1. Inputs of the AND gate 158 are coupled, respectively, to an output of the respective SR via a second node N2, and to a TEn signal line 164. An output of the AND gate 158 is coupled to a control input of the T-SW 156 to activate or deactivate the T-SW 156.
An input of the TSV 102(1,3) is coupled to a D-SW normal node 152(1,3) of the D-SW 150(1,3) via a first node N1(1,3). An input of the D-SW 150(1,3) is coupled to an access control logic via an access control logic line 168(1,3). The D-SW normal node 152(1,3) is coupled to the TSV 102(1,3) via the first node N1(1,3). The domino node 154(1,3) is coupled to a TSV 102(1,4) via the D-SW line and via the first node N1(1,4).
The D-SW normal node 152 of the D-SW 150 may be coupled to the TSV 102 via a first node N1. The domino node 154 of the D-SW 150 may be coupled to the TSV 102 of an adjacent domino switch circuit, via a D-SW line and via the first node N1 of the adjacent domino switch circuit. A control input of the D-SW 150 is coupled to an output of the respective SR via a second node N2. An input and an output of the T-SW 156 may be coupled, respectively, to a Vdd/Vss signal line 166, and to the TSV 102 via the first node N1. Inputs of the AND gate 158 are coupled, respectively, to an output of the respective SR via a second node N2, and to a TEn signal line 164. An output of the AND gate 158 is coupled to a control input of the T-SW 156 to activate or deactivate the T-SW 156.
An input of the TSV 102 is coupled to a D-SW normal node 152 of the D-SW 150 via a first node N1. An input of the D-SW 150 is coupled to an access control logic via an access control logic line 168. The D-SW normal node 152 is coupled to the TSV 102 via the first node N1. The domino node 154 is coupled to a TSV 102 of an adjacent domino switch circuit via the D-SW line and via the first node N1 of the adjacent domino switch circuit.
The D-SW 150 may be switched to one of a normal mode and a domino mode. A control input of the D-SW 150 receives a signal from the respective SR via the second node N2. The signal received by the control input of the D-SW 150 is provided to the SR 108(3) from a register line 120. The D-SW 150 in the normal mode is controlled by an inactive signal received from the respective SR via the second node N2. A signal on the access control logic line 168 is provided, via a switch arm of the D-SW 150 coupled to the D-SW normal node 152 in the normal mode, to the TSV 102 via the first node N1. The D-SW 150 receives the signal on the access control logic line 168, and provides the signal to the TSV 102 via the switch arm of the D-SW 150 coupled to the D-SW normal node 152 and via the first node N1. In other words, the switch arm of the D-SW 150 is coupled to the D-SW normal node 152 responsive to the inactive signal received from the respective SR via the second node N2.
In the domino mode, the switch arm of the D-SW 150 is controlled by an active signal received from the respective SR via the second node N2. The signal on the access control logic line 168 is provided to the TSV 102 of an adjacent domino switch circuit via the switch arm of the D-SW 150 coupled to the D-SW domino node 154, and via the first node N1 of the adjacent domino switch circuit. In other words, the D-SW 150 receives the signal on the access control logic line 168 and provides the signal to the TSV 102 of the adjacent domino switch circuit via the switch arm of the D-SW 150 coupled to the D-SW domino node 154 and via the first node N1 of the adjacent domino switch circuit. The switch arm of the D-SW 150 is coupled to the D-SW domino node 154 responsive to the active signal received from the respective SR via the second node N2. In a case where a D-SW 150 of a previous domino switch circuit is also in the domino mode, a signal on an access control logic line 168 of the previous domino switch circuit is provided to the TSV 102 via a switch arm of a D-SW 150 of the previous domino switch circuit coupled to a D-SW domino node 154 of the previous domino switch circuit, via a D-SW line, and via the first node N1.
The switch arm of the T-SW 156 may be controlled to be open when the T-SW 156 is turned off responsive to an inactive signal output by the AND gate 158. A signal output by the AND gate 158 is inactive when at least one of a signal output by the respective SR and the signal on the TEn signal line 164 is inactive.
The switch arm of the T-SW 156 may be controlled to be closed when the T-SW 156 is turned on responsive to an active signal output by the AND gate 158. The signal output by the AND gate 158 is active when both of the signal output by the respective SR and the signal on the TEn signal line 164 are active.
The active signal on the TEn signal line 164 may be provided to the control input of the T-SW 156 via the AND gate 158 when the signal output by the respective SR is active, to thereby provide the signal on the Vdd/Vss signal line 166 to the TSV 102 via the closed switch arm of the T-SW 156.